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data brief for further information contact your local stmicroelectronics sales office. june 2008 rev 3 1/26 1 spc560p50l3, spc560p50l5 spc560p44l3, spc560p44l5 32-bit power architecture? based mcu for chassis & safety applications features high performance 60mhz e200z0h cpu ? 32bit power architecture tm book e cpu ? variable length encoding (vle) memory available ? 512kbyte on-chip flash memory, with ecc, with erase/program controller ? 4x16kbyte on-chip flash memory with ecc for eeprom emulation ? 40kbyte on-chip ram with ecc fail safe protection ? programmable watchdog timer ? junction temperature sensor ? non maskable interrupt ? fault collection unit nexus l2+ interface interrupts ? 16 channel edma controller ? 16 priority level controller two general purpose etimer units ? 6 timers each with up / down capabilities ? 16bit resolution, cascadeable counters ? quadrature decode with rotation direction flag ? double buffer input capture and output compare communications interfaces ? two linflex channels ? four dspi channels with automatic chip select generation ? one flexcan interface (2.0b active) with 32 message objects ? one safety port based on flexcan with 32 message objects and up to 7.5mbit/s capability; usable as 2 nd can when not used as safety port ? flexray module (v2.1) with dual or single channel two 10-bit a/d converter ? 2 x 13 input channels ? conversion time < 1us including sampling time at full precision ? programmable adc cross triggering unit (ctu) ? 4 analog watchdog with interrupt capability on chip can/uart/fle xray bootstrap loader with boot assist module (bam) one flexpwm unit ? 8 complementary or independent outputs with adc synchronisation signals ? integrated configurable dead time unit and inverter fault input pins ? 16bit resolution, up to 2x f cpu clock generation ? 4-40mhz main oscillator ? 16mhz internal rc-oscillator ? software controlled fmpll voltage supply ? 3.3v or 5v supply for i/os and adc ? on chip single supply voltage regulator with external ballast transistor temperature range ? operating temperature range -40 to 125c or -40 to 105c lqfp-144 lqfp-100
spc560p50x, spc560p44x contents 2/26 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 overview of the spc560px . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3.1 high performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3.3 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . 9 3.3.4 on-chip flash memory with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3.5 on-chip sram with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.6 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.7 system clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.8 frequency modulated pll (fmpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.9 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.10 internal rc-oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.11 periodic interrupt timer module (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.12 system timer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.13 software watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.14 fault collection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.15 system integration unit (siu-lite) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.16 boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.17 miscellaneous control module (mcm) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.18 can (flexcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.19 safety port (flexcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.20 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.21 serial communication interface module (linflex) . . . . . . . . . . . . . . . . . 15 3.3.22 deserial serial peripheral interface (dspi) module . . . . . . . . . . . . . . . . 16 3.3.23 flexpwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.24 etimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.25 analog to digital converter module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.26 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
contents spc560p50x, spc560p44x 3/26 3.3.27 junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.28 nexus development interface (ndi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.29 ieee 1149.1 jtag controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.30 on-chip voltage regulator (vreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 electric power steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 airbag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 developer environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
spc560p50x, spc560p44x 4/26 1 introduction the 32-bit spc560px automotive microcontroller is a system-on-chip (soc) device designed to be central to the development of the next wave of airbag/steering applications. the spc560px is one of a series of next-generation automotive microcontrollers based on the power architecture? book e architecture and designed specifically for embedded applications. this document describes the features of th e spc560px and highlights important electrical and physical characteristics of the device.
spc560p50x, spc560p44x 5/26 2 block diagram figure 1 shows a top-level block diagram of the spc560px microcontroller. figure 1. spc560px block diagram e200z0 core 32-bit general purpose registers special purpose registers integer execution unit exception handler variable length encoded instructions instruction unit load/store unit branch prediction unit jtag nexus 2+ 1.2 v regulator control xosc 16 mhz rc-oscillator fmpll_0 (system) fmpll_1 (flexray, motctrl) nexus port controller interrupt controller flexray dma2x 16 channels master master instruction 32-bit master data 32-bit master 512 kb code flash ecc 64 kb data flash ecc 40 kb sram ecc system integration unit-lite boot assist module pit stm swt slave slave slave crossbar switch (xbar, amba 2.0 v6 ahb) peripheral bridge flexpwm ctu 1.2 v rail vreg 2 4 ch. 11 4 11 junc. temp. sensor 2 4 2 flexcan mcm safety port fault collection unit cancontroller area network (flexcan) dspideserial serial peripheral interface linflexserial communication interface (lin support) fmpllfrequency-modulated phase-locked loop sramstatic random-access memory flexpwmflexible pulse width modulation etimerenhanced timer pitperiodic interrupt timer adc etimer (6ch) dspi linflex
spc560p50x, spc560p44x 6/26 3 overview of the spc560px the following sections provide high-level descriptions of the features found on the spc560px. 3.1 device summary table 1. spc560px device summary feature spc560p44 spc560p50 flash memory size with ecc (kb) 384 576 ram size with ecc (kb) 32 40 processor core 32-bit e200z0 cpu performance static ? 60 mhz analog-to-digital converters (adc) 2 (10-bit, 13-channel) dspi (deserial serial peripheral interface) modules 4 enhanced dma (direct memory access) channels 16 etimer modules 2 (6 channel) flexcan (controller area network) yes (1) 1. 32 message buffers flexpwm (pulse-width modulation) channels 8 flexray ? yes (2) 2. 32 message buffers, dual-channel fmpll (frequency-modulated phase-locked loop) modules 12 intc (interrupt controller) channels 100 144 jtag interface yes junction temperature sensor yes linflex modules 2 nexus port controller (npc) yes (level 2+) pit (periodic interrupt timer) yes packages lqfp100 lqfp144
spc560p50x, spc560p44x 7/26 3.2 feature list single issue, 32-bit power architecture ? cpu core complex (e200z0) with harvard architecture: ? provides variable length encoding (vle) instruction set encoding for code size footprint reduction. ? with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional book e compliant code. up to 512 kb on-chip code flash memory with ecc plus 64 kb on-chip data flash with ecc up to 40 kb sram on-chip with ecc intc - interrupt controller capable of handling 144 selectable-priority interrupt sources up to two fmpll modules clock monitor unit (cmu) to m onitor the integrity of the ma in crystal oscillator and the pll and act as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock rcosc - 16 mhz internal rc oscillator (trimmable) pit - four periodic interrupt time rs with 32-bit counter resolution swt - windowed software watchodog stm - output compare system timer to support autosar task protection xbar - crossbar switch arch itecture for concurrent ac cess to peripherals, flash memory or ram from multiple bus masters (amba 2.0 v6 ahb) edma - 16 channel enhanced direct memory access controller with multiple transfer request sources using dma mux siu-lite - system integration unit lite; controls the gpio mode of the pads, the pads alternate function, and the pads configuration bam - boot assist module supports downloading operation to internal sram via serial link (flexcan or linflex or flexray) flexpwm - motor control pwm module (1 x 8pwm channels) etimer - two enhanced timer modules (6 channels each) with dedicated motor control and quadrature decode features integrated safety port - to support functional safety architectures on the ecu level. can be optionally used as a second flexcan module with 32 message buffers. adc - two 10-bit analog-to-digital converters, conversion time <1 s ctu - flexpwm to adc and etimer cross triggering unit fcu - fault collection unit for functional safety dspi - four serial peripheral interface modules linflex - two serial communication interface modules with lin support flexcan - controller area network module with 32 message buffers flexray - dual channel flexray controller with 32 message buffers gpio ? 144-pin package: 82 general-purpose pins supporting input/output operations plus 26 general-purpose pins supporting input operations (108 in total). out of these 108 pins, 32 have external interrupt capability.
spc560p50x, spc560p44x 8/26 ? 100-pin package: 51 general-purpose pins supporting input/output operations plus 16 general-purpose pins supporting input operations (67 in total). out of these 67 pins, 25 have extern al interrupt capability. ndi - nexus development interface per ieee-isto 5001-2003 standard class 2+ ieee 1149.7 class 4 (narrow pin interface) to allow optimized device i/o count ? backward compatible to jtag (ieee 1149.1) jtag (ieee 1149.1) 4 pin interface vreg - voltage regulator for regulation into 3.3v input down to 1.2v nominal core logic level with external transistor embedded junction temperature sensor 3.3 feature details 3.3.1 high performance e200z0 core processor the e200z0 power architecture tm core provides the following features: high performance e200z0 core processor for managing peripherals and interrupts single issue 4-stage pipeline in-order execution 32-bit power architecture tm cpu harvard architecture variable length encoding (vle), allowing mixed 16-bit and 32-bit instructions ? results in smaller code size footprint ? minimizes impact on performance branch processing acceleration using lookahead instruction buffer load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles thirty-two 32-bit general purpose registers (gprs) separate instruction bus and load/store bus harvard architecture hardware vectored interrupt support reservation instructions for implementing read-modify-write constructs long cycle time instructions, except for guarded loads, do not increase interrupt latency extensive system development support through nexus debug port non maskable interrupt support 3.3.2 crossbar switch (xbar) the xbar multi-port crossbar s witch supports simultaneous connections betw een 4 master ports and 3 slave ports. the crossbar supports a 32-bit address bus width and a 32-bit data bus width. the crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers must be an instruction fetch from internal flash memory. if a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority ma ster and grant it ownersh ip of the slave port. all other masters requesting that slave port will be stalled until the hig her priority master
spc560p50x, spc560p44x 9/26 completes its transactions. requesting master s will be treated with equal priority and will be granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. the crossbar provides the following features: 4 master ports: ? e200z0 core complex instruction port ? e200z0 core complex load/store data port ?edma ?flexray 3 slave ports: ? flash memory (code flash and data flash) ?sram ? peripheral bridge 32-bit internal address, 32-bit internal data paths fixed priority arbitration based on port master temporary dynamic priority elevation of masters 3.3.3 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall block size. the edma module provides the following features: 16 channels support independent 8, 16 or 32 bit single value or block transfers supports variable sized queues and circular queues source and destination address registers are independently configured to post- increment or remain constant each transfer is initiated by a peripheral, cpu, or edma channel request each edma channel can optionally send an interrupt request to the cpu on completion of a single value or block transfer dma transfers possible between system me mories, dspi?s, adc, flexpwm, etimer and ctu programmable dma channel mux allows assignment of any dma source to any available dma channel with up to a total of 30 potential request sources. edma abort operation through software 3.3.4 on-chip flash memory with ecc the spc560px provides up to 576 kb of programmable, non-volatile, flash memory. the non-volatile memory (nvm) can be used for instruction and/or data storage. the flash memory module interfaces the system bus to a dedicated flash memory array controller. it supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to
spc560p50x, spc560p44x 10/26 flash memory. the module contains a four-entry, 4x128-bit prefetch buffers. prefetch buffer hits allow no-wait responses. normal flash memory array accesses are registered and are forwarded to the system bus on the following cycle, incurring 3 wait-states. the flash memory module provides the following features: up to 576 kb flash memory ? 8 blocks (32kb + 216kb + 32kb + 32kb + 3x128kb) code flash ? 4 blocks (16kb + 16kb + 16kb + 16kb) data flash ? full read while write capability between code and data flash four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to prefetch code or data or both) typical flash memory access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at 60 mhz hardware managed flash memory writes handled by 32-bit risc krypton engine hardware and software configurable read and write access protections on a per-master basis. configurable access timing allowing use in a wide range of system frequencies. multiple-mapping support and mapping-based block access timing (0?31 additional cycles) allowing use for emulation of other memory types. software programmable block program/erase restriction control. erase of selected block(s) read page size of 128 bits (4 words) 64-bit ecc with single-bit correction, do uble-bit detection for data integrity embedded hardware program and erase algorithm erase suspend, program suspend and erase-suspended program censorship protection scheme to prev ent flash memory content visibility hardware support for eeprom emulation 3.3.5 on-chip sram with ecc the spc560px sram module provides a general-purpose memory of up to 40 kb in total. ecc handling is done on a 32-bit boundary and is completely software compatible with spc560px family devices with an e200z6 core and 64-bit wide ecc. the sram module provides the following features: supports read/write accesses mapped to the sram memory from any master 40 kb general purpose ram supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory typical sram access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block 3.3.6 interrupt controller (intc) the intc (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems.
spc560p50x, spc560p44x 11/26 for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be executed. it also provides an ample number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. the intc provides the following features: unique 9-bit vector for each separate interrupt source 8 software triggerable interrupt sources 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source ability to modify the is r or task priority. ? modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. two external high priority interrupts directly accessing the main core and iop critical interrupt mechanism 3.3.7 system clocks and clock generation the following list summarizes the system clock and clock generation on the spc560px: lock detect circuitry continuously monitors lock status loss of clock (loc) detection for pll outputs programmable output clock divider ( 1, 2, 4, 8) flexpwm module and etimer module can run on an independent clock source on-chip oscillator with auto matic level control (tbc) internal 16-mhz rc-oscillator for rapid start-up and safe mode ? supports frequency trimming by user application 3.3.8 frequency modulated pll (fmpll) the fmpll allows the user to generate high speed system clocks from an 4mhz to 40mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software configurable. the pll has the following major features: input clock frequency from an 4mhz to 40mhz voltage controlled oscillator (vco ) range from 256mhz to 512mhz reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock frequency modulated pll ? modulation enabled/disabled through software
spc560p50x, spc560p44x 12/26 ? triangle wave modulation programmable modulation depth (0.25% to 4% deviation from center frequency) ? programmable modulation frequency dependent on reference frequency self-clocked mode (scm) operation 3.3.9 main oscillator the main oscillator prov ides these features: input frequency range 4 mhz - 40 mhz crystal input mode or oscillator input mode pll reference 3.3.10 internal rc-oscillator this device has an rc ladder phas e-shift oscillator. the architec ture uses constant current charging of a capacitor. the voltage at the capacitor is compared by the stable bandgap reference voltage. the rc oscillator provides these features: nominal frequency 16mhz +/-5% variation over voltage and temperature after process trim clock output of the rc oscillato r serves as system clock sour ce in case loss of lock or loss of clock is detected by the pll rc-oscillator is used as the defa ult system clock during startup 3.3.11 periodic interr upt timer module (pit) the pit module implements these features: up to four general purpose interrupt timers 32-bit counter resolution clocked by system clock frequency each channel can be used as trigger for a dma request 3.3.12 system timer module the stm module implements these features: one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode 3.3.13 software watchdog timer the swt has the following features: ? 32-bit time-out register to set the time-out period ? programmable selection of system or oscillator clock for timer operation ? programmable selection of window mode or regular servicing ? programmable selection of reset or interrupt on an initial time-out
spc560p50x, spc560p44x 13/26 ? master access protection ? hard and soft configuration lock bits ? reset configuration inputs allow timer to be enabled out of reset 3.3.14 fault collection unit the fcu provides an indipendent fault reporting mechanism even in case the cpu is misbehaving. the fcu module has the following features: fcu status register reporting the device status continuous monitoring of critical fault signals user selection of critical signals from different fault sources inside the device critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device and/or other circuitry (ex: safety relay, flexray transceiver) faults are latched into a register 3.3.15 system integr ation unit (siu-lite) the spc560px siu-lite controls mcu pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the siu provides the following features: centralized general purpose input output (gpio) control of up to 82 input/output pins and 26 analog input only pads (package dependent) all gpio pins can be independently configured to support pull-up, pull down, or no pull reading and writing to gpio supported both as individual pins and 16-bit wide ports all peripheral pins, except adc channels, can be alternatively configured as both general purpose input or output pins adc channels support alternative configuration as general purpose inputs direct readback of the pin value is supported on all pins through the siu configurable digital input filter that can be applied to some general purpose input pins for noise elimination ? up to four internal functions can be multiplexed onto 1 pin 3.3.16 boot and censorship different booting modes are available in the spc560px: booting from internal flash memory and booting via a serial link. the default booting scheme is the one which us es the internal flash memory (an internal pull-down is used to select this mode). the alternate option allows the user to boot via flexcan or linflex (using the boot assist module software) or via flexray. a censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device.
spc560p50x, spc560p44x 14/26 a password mechanism is designed to grant the legitimate user access to the non volatile memory. boot assist module (bam) the bam is a block of read-only one-time programmed memory and is identical for all spc560px devices that are based on the e200z0h core. the bam program is executed every time the device is powered-on if the alternate boot mode has been selected by the user. the bam provides the following features: serial bootloading via flexcan or linflex or flexray. bam can accept a password via the used serial communication channel to grant the legitimate user access to the non volatile memory. 3.3.17 miscellaneous c ontrol module (mcm) the mcm on this device features the following: platform configuration & revision ecc error reporting for flash memory and sram ecc error injection for ram 3.3.18 can (flexcan) the spc560px mcu contains one controller area network (flexcan) module. this module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. flexcan module contains 32 message buffers. the flexcan module provides the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1mbit/s 32 message buffers of zero to eight bytes data length each message buffer configurable as rx or tx, all supporting standard and extended messages programmable loop-back mode supporting self-test operation three programmable mask registers programmable transmit-first scheme: lowest id or lowest buffer number time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts independent of the transmission medium (an external transceiver is assumed) high immunity to emi short latency time due to an arbitration scheme for high-priority messages
spc560p50x, spc560p44x 15/26 transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to message id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification receive features ? individual programmable filters for each mailbox ? eight mailboxes configurable as a six-entry receive fifo ? eight programmable acceptance filters for receive fifo programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter 3.3.19 safety port (flexcan) the spc560px mcu has a second can controller synthesized to run at high bit rates to be used as a safety port. the can module of the safety port provides the following features: identical to the flexcan module bit rate up to 7.5 mb at 60 mhz cpu clock using direct connection between can modules (no physical transceiver required) 32 message buffers of zero to eight bytes data length can be used as a second independent can module 3.3.20 flexray the flexray module provides the following features: full implementation of flexray protocol specification 2.1 32 configurable message buffers can be handled dual channel or single channel mode of operation, each at up to 10mbit/s data rate message buffers configurable as tx, rx or rxfifo message buffer size configurable message filtering for all message buffers based on frameid, cycle count and message id programmable acceptance filters for rxfifo message buffers 3.3.21 serial communication interface module (linflex) the linflex on the spc560px features the following: supports lin master mode, lin slave mode and uart mode lin state machine compliant to lin1.3, 2.0 and 2.1 specifications handles lin frame transmission and reception without cpu intervention lin features ? autonomous lin frame handling ? message buffer to store identifier and up to eight data bytes
spc560p50x, spc560p44x 16/26 ? supports message length of up to 64 bytes ? detection and flagging of lin errors: sync field; delimiter; id parity; bit, framing; checksum and time-out errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features: loop back; self test; lin bus stuck dominant detection ? interrupt-driven operation with 16 interrupt sources lin slave mode features ? autonomous lin header handling ? autonomous lin response handling uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt-driven operation with four interrupt sources ? separate transmitter and receiver cpu interrupt sources ? 16-bit programmable baud-rate modulus counter and 16-bit fractional ? two receiver wake-up methods 3.3.22 deserial serial peri pheral interface (dspi) module the deserial serial peripheral interface (dspi) module provides a synchronous serial interface for communication between the spc560px mcu and external devices. the dspi modules provide these features: full duplex, synchronous transfers master or slave operation programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag programmable transfer baud rate programmable data frames from 4 to 16 bits up to 4 chip select lines available, depending on package and pin multiplexing, enable 12 external devices to be selected using external muxing from a single dspi 8 clock and transfer attributes registers chip select strobe available as alternate function on one of the chip select pins for de- glitching fifos for buffering up to 4 transfers on the transmit and receive side queueing operation possible through use of the i/o processor or edma general purpose i/o functionality on pins when not used for spi
spc560p50x, spc560p44x 17/26 3.3.23 flexpwm the pulse width modulator module (pwm) contains four pwm submodules each of which is set up to control a single half-bridge power stage. there are also four fault channels. this pwm is capable of controlling most mo tor types: ac induction motors (acim), permanent magnet ac motors (pmac), both brushless (bldc) and brush dc motors (bdc), switched (srm) and variable reluctance motors (vrm), and stepper motors. the flexpwm block implements the following features: 16 bits of resolution for center, edge aligned, and asymmetrical pwms pwm outputs can operate as complimentary pairs or independent channels can accept signed numbers for pwm generation independent control of both edges of each pwm output synchronization to external hardware or other pwm supported double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability multiple adc trigger events can be generated per pwm cycle via hardware write protection for critical registers fault inputs can be assigned to control multiple pwm outputs programmable filter s for fault inputs independently programmable pwm output polarity independent top and bottom deadtime insertion each complementary pair can operate with its own pwm frequency and deadtime values individual software-control for each pwm output all outputs can be programmed to change simultaneously via a "force out" event pwmx pin can optionally output a third pwm signal from each submodule channels not used for pwm generation can be used for buffered output compare functions channels not used for pwm generation can be used for input capture functions enhanced dual edge capture functionality edma support with automatic reload 3.3.24 etimer six 16-bit general purpose up/down timer/counter per module are implemented with the following features: individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0% - 100% pulse measurement
spc560p50x, spc560p44x 18/26 ? rotation direction flag (quad decoder mode) maximum count rate counters are cascadeable programmable count modulo quadrature deco de capabilities counters can share available input pins count once or repeatedly counters are pre-loadable pins available as gpio when timer functionality not in use 3.3.25 analog to digi tal converter module the adc module provides the following features: analog part: two on-chip ad converters ? 10 bit ad resolution ? one sample and hold unit per adc ? conversion time, including sampling time, less than 1 s (at full precision) ? typical sampling time is 150 ns min. (at full precision) ? dnl/inl 1lsb ? tue <1.5lsb ? single-ended input signal range from 0 to 3.3v - ? the adc and its reference can be supplied with a voltage independent from v ddio ? the adc supply can be equal or higher than v ddio ? the adc supply and the adc reference are not independent from each other (they are internally bonded to the same pad) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles digital part: 2x13 input channels ? the total 26 channels includes 4 channels shared among the two converters four analog watchdogs comparing adc results against predefined levels (low, high, range) before results are stored in the appropriate adc result location, 2 modes of operation: motor control mode or regular mode regular mode features ? register based interface with the cpu: control reg., status reg., 1 result register per channel ? adc state machine managing 3 request flows: regular command, hardware injected command, software injected command ? selectable priority between software and hardware injected commands ? 4 analog watchdogs comparing adc results against predefined levels (low, high, range) ? dma compatible interface motor control mode features
spc560p50x, spc560p44x 19/26 ? triggered mode only ? four independent result queues (1x16 entries, 2x8 entries, 1x4 entries) ? result alignment circuitry (lef t justified; ri ght justified) ? 32-bit read mode allows to have channel id on one of the 16-bit part ? dma compatible interfaces 3.3.26 cross triggering unit (ctu) the cross triggering unit (ctu) allows automa tic generation of adc conversion requests on user selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration. it implements the following features: double buffered trigger generation unit with up to eight independent triggers generated from external triggers trigger generation unit configurable in sequential mode or in triggered mode each trigger can be appropriately delayed to compensate the delay of external low pass filter double buffered global trigger unit allowing etimer synchronization and/or adc command generation double buffered adc command list pointers to minimize adc-trigger unit update double buffered adc conversion command list with up to 24 adc commands each trigger has the capability to generate consecutive commands adc conversion command allows to control adc channel from each adc, single or synchronous sampling, independent result queue selection 3.3.27 junction temperature sensor the spc560px has a junction temperature sensor to allow to measure, by the adc, the temperature of the silicon. these are the key parameters of the junction temperature sensor: nominal temperature range from -40c to +150c accuracy of the sensor +/- 5c (tbc) 3.3.28 nexus developm ent interface (ndi) the ndi (nexus debug interface) block provid es real-time development support capabilities for the spc560px power architecture based mcu in compliance with the ieee-isto 5001- 2003 standard. this development support is supplied for mcus without requiring external address and data pins for internal visibility. the ndi block is an integration of several individual nexus blocks that are selected to provide the development support interface for this device. the ndi block interfaces to the host processor and internal busses to provide development support as per the ieee-is to 5001-2003 class 2+ standard. the development support provided includes access to the mcus internal memory map and access to the processors internal registers during run time. the nexus interface provides the following features: configured via the ieee 1149.1 all nexus port pins operate at v ddio (no dedicated power supply)
spc560p50x, spc560p44x 20/26 nexus 2+ features supported ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory mapped resources through jtag pins ? overrun control, which selects whether to stall before nexus overruns or keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing auxiliary output port ? 4 mdo (message data out) pins ? 1 mcko (message clock out) pin ? 2 mseo (message start/end out) pins ?1 evto (event out) pin auxiliary input port ?1 evti (event in) pin 3.3.29 ieee 1149.1 jtag controller the jtag controller (jtagc) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. the jtag controller provides the following features: ieee test access port (tap) interface 4 pins (tdi, tms, tck, tdo) selectable modes of operation include jtagc/debug or normal system operation. a 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass, idcode, extest, sample, sample/preload a 5-bit instruction register that supports the additional followin g public instructions: ? access_aux_tap_npc, access_aux_tap_once three test data registers: a bypass register, a boundary scan register, and a device identification register. the size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths. a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry. 3.3.30 on-chip volt age regulator (vreg) the on-chip voltage regulator module provides the following features: uses external npn transistor regulates external 3.3v down to 1.2v for the core logic low voltage detection on the internal 1.2v and i/o voltage 3.3v
spc560p50x, spc560p44x 21/26 4 application examples 4.1 electric power steering figure 2 outlines a typical electric power steering application built around the spc560px microcontroller. figure 2. electric power steering application position sensor gearbox sensor load position sensor physical layer torque relay relay driver signal conditioning circuitry driver pwm 3 phase low voltage power stage pmsm signal conditioning circuitry driver reverse bat protection flexray fast adc <1 s, 10 bit timer safety port core flexcan faults motor control pwm 10 ns res dspi spc560px vcc vanalog vref vcc vanalog vref id system basis chip windowed watchdog hi-speed can physical layer can complex hardware watchdog input modules output drivers (valves, pump) sensors n n safety relay u dc bus
spc560p50x, spc560p44x 22/26 4.2 airbag figure 3 outlines a typical airbag application built around the spc560px microcontroller. figure 3. airbag application spi physical interface physical interface physical interface physical interface satellite i/f satellite i/f satellite i/f satellite i/f buckle i/f buckle i/f v ign safing unit power supply control chain dspi adc flexcan linflex dspi dspi x/y - accel. can physical layer lin physical layer body network (dashboard) occupant detection 4-ch squib driver v boost squib 1 squib 2 squib 3 squib 4 custom device v boost v buck v logic v io spc560px
spc560p50x, spc560p44x 23/26 5 developer environment the following development support will be available: automotive evaluation boards (evb) f eaturing can, lin in terfaces and more compilers debuggers jtag and nexus interfaces autocode generation tools initialization tools the following software support will be available: core and peripheral self tests note: 1 lbga208 available only as development package for nexus2+
spc560p50x, spc560p44x 24/26 6 ordering information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at http://www.st.com . figure 4. commercial product code structure table 2. order codes (1) order code flash (kb) sram (kb) package characteristics spc560p50l5cefa 576 40 lqfp144 data flash; flexray; 5 v spc560p50l5cefb 576 40 lqfp144 data flash; flexray; 3.3 v spc560p50l3cefa 576 40 lqfp100 data flash; flexray; 5 v spc560p50l3cefb 576 40 lqfp100 data flash; flexray; 3.3 v spc560p44l5cefa 384 32 lqfp144 data flash; flexray; 5 v spc560p44l5cefb 384 32 lqfp144 data flash; flexray; 3.3 v spc560p44l3cefa 384 32 lqfp100 data flash; flexray; 5 v SPC560P44L3CEFB 384 32 lqfp100 data flash; flexray; 3.3 v 1. all parts support a maximum speed of 60 mhz and a temperature range of -40 c to +125 c. memory conditioning core family y = tray r = tape and reel x = tape and reel 90 e = optional 4x16 kbyte data flash available for eeprom emulation f = optional flexray controller a = 60 mhz, 4 dspi, 5 v b = 60 mhz, 4 dspi, 3.3 v a = -40 to +85c b = -40 to +105c c = -40 to +125c l3 = lqfp100 l5 = lqfp144 50 = 512 kb 44 = 384 kb p=pictus 0 = e200z0 spc56 = powerpc in 90nm temperature package custom vers. spc56 50 y 0p c l5 efa example code: product identifier
spc560p50x, spc560p44x 25/26 7 document revision history table 3. revision history date revision changes 12-nov-2007 1 initial release 16-may-2008 2 added 64-pin in pin muxing, pin mapping and mechanical data 13-jun-2008 3 removed 64-pin, changed the contents and added new rpns.
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